1. Technical Field
Various embodiments generally relate to a semiconductor apparatus, and more particularly to an internal strobe signal generating circuit capable of selecting data rate and semiconductor apparatus including the same.
2. Related Art
A semiconductor apparatus such as a processor and semiconductor memories (e.g., DRAM) may receive and output data in synchronization with a clock signal. The single data rate (SDR) scheme allows the semiconductor apparatus to receive data in synchronization with a rising edge of the clock signal. As the operation speed of the semiconductor apparatus becomes faster, the double data rate (DDR) scheme has been proposed to allow the semiconductor apparatus to receive data in synchronization with both the rising and falling edges of the clock signal.
The semiconductor apparatus uses a data strobe signal as the clock signal for receiving the data. The data strobe signal may have the same period as a clock signal. As the operation speed of the semiconductor apparatus becomes faster, the frequency of a system clock signal used for the communication between a host and a memory apparatus increases. As a result, the pulse width of the data strobe signal for receiving the data becomes narrower, and thus the timing margin for receiving the data becomes smaller.